Test systems used for testing semiconductor devices should be able to test each new generation of devices at the maximum speed of the new device. A testing apparatus for a digital circuit generates various waveforms at a desired timing and detects the voltage level of the waveforms, usually comparing data read from the device under test with what is expected. The timing system is one of the most critical specifications of a tester. At present, typical systems provide a 60-ps resolution, 500-ps maximum driver-to-driver skewing and 700-ps maximum edge placement error. The overall timing accuracy is within .+-.1.5 ns. For the new generation of high-speed devices, the accuracy should be within a few hundred picoseconds. To achieve this increased accuracy, it is essential to calibrate the timing of the testing apparatus.
The invention is particularly appropriate for memory devices. Semiconductor memories tend to have a large number of input and output pins, for example, 36 pins, and are tested 16 or 32 at a time, requiring 36.times.32 tester pins. Consequently, the tester requires a large number of units of a per-pin structure, each of which needs timing calibration, since it is necessary to ensure that the timing of all voltage transitions delivered to the pins of the DUT, and the time at which data output from the device is compared with expected data, are accurate in relation to a defined reference. However, these transitions often occur at different times, due to the fact that signals travelling a channel path to a DUT must pass through cables, formatters, drivers and other devices having different electrical characteristics. The resulting timing variations are called "skew". Generally, calibration involves measuring the skew in each system input and output channel and compensating for it by means of a variable delay in each channel (e.g., see U.S. Pat. No. 5,274,796). Hardware, software and a combination thereof can be used to control the compensating delay.
The traditional approach involves serially calibrating tester pin timing with respect to a reference pin or an external reference (see, e.g. U.S. Pat. No. 5,712,855). Since pin calibration measurements must be performed sequentially, an enormous amount of time is needed for this method. The amount of measured data required is also large; thus, the transfer and calculation time is undesirably long.
Another conventional approach which alleviates the above problems is described in U.S. Pat. No. 5,477,139, wherein the calibration is performed in parallel. This method shortens the time required for timing measurements, however, it increases the cost of the whole measuring apparatus, as it uses a number of local sequencers, one for each pin of the device under test (DUT).
Another means to execute the skew adjustment in parallel for all terminals of the IC tester is described in EP 356,967 A2. The disadvantage of the known method is that the skew adjustment is performed manually by an operator.
Another widely used calibration technique uses time domain reflectometry (TDR) based on transmission line theory. According to this theory, a wave travelling through a transmission line terminated by anything other than the line's characteristic impedance is reflected back through the line. If the line terminates with an open circuit, the reflected wave equals the forwarded wave and this reflected wave is detected by the pin electronics. Using TDR techniques, automatic calibration circuits are provided to measure channel delays to the open circuited contact points of the tester. However, this approach has the disadvantage of requiring many delay compensation circuits per pin driver.
A method of autocalibrating a tester's timings with respect to a common reference point is described in "Maximising and maintaining AC test accuracy in the manufacturing environment" by R. J. Bulaga and E. F. Westermann, Proceedings of the International Test Conference, Nashville, 1991, p.p. 976-985, IEEE. However, the known method is adapted for calibrating the skew of non-cyclic, e.g. asynchronous, test signals, requires the use of multiple bulk hardware and makes the system dense, and cost-ineffective. It takes about 30 seconds to perform a complete calibration, which is slow for conventional memories.
An automatic skew calibration circuit described in U.S. Pat. No. 5,384,781 provides a calibration technique for multi-channel signal sources using a means for varying the delay in response to a skew signal and determining a calibrated value for the delay. The circuit comprises a pair of cross-coupled flip-flops and a microprocessor. This method takes account of the variations in the time at which different flip-flops change state. It provides a fast calibration method which may be performed easily and frequently to correct the skew errors in signal sources. However, the technique becomes extremely complicated when the number of signal sources increases; moreover, it is not cost-effective in semiconductor memory test equipment with a large number of signal sources.
One of the main limitations of the known approaches to signal skew calibration is that the accuracy of measuring the signal skew decreases with the increasing speed and complexity of each new generation of high-speed synchronous devices. In a modern context, not only input/output signal skew compensation is needed, but also a significant improvement in the accuracy of measuring the skew itself, where there are multiple error sources and skew compensating delays. The necessity of increasing the accuracy of skew calibration creates a requirement for a fast, automatic calibration system providing extremely precise automatic calibration in test systems with multiple signal sources.